1. Field of the Invention
The present invention relates to a semiconductor manufacturing process, and more particularly to a manufacturing process for an embedded semiconductor device.
2. Description of Related Art
As shown in FIG. 1, a conventional chip package structure 100 having a cavity mainly includes a carrier 110, a first chip 120, a second chip 130, and an encapsulant 140. The carrier 110 is usually composed of a substrate 111 and a heat dissipating plate 112. The substrate 111 has an upper surface 113, a bottom surface 114, and an opening 115. The heat dissipating plate 112 is adhered to the bottom surface 114 of the substrate 111, such that the opening 115 of the substrate 111 forms the cavity capable of accommodating chips. A plurality of first pads 116 and a plurality of second pads 117 are disposed on the upper surface 113 of the substrate 111. The first chip 120 is electrically connected to the first pads 116 via a plurality of first conductive wires 150. The second chip 130 is adhered to the first chip 120 and electrically connected to the second pads 117 through a plurality of second conductive wires 160. The encapsulant 140 covers the first chip 120 and the second chip 130 and encapsulates the first conductive wires 150 and the second conductive wires 160.
Note that the first pads 116 and the second pads 117 are required to be disposed on the same surface of the substrate 111. Hence, wire-bonding heights of the first conductive wires 150 and the second conductive wires 160 must be precisely controlled, so as to prevent the occurrence of short circuit caused by an excessively close wire-bonding distance or by a molding flow affecting the wires during a process of molding the encapsulant. As such, the second chip 130 is at a higher level than the upper surface 113 of the substrate 111, and thereby the wire-bonding height of the second conductive wires 160 is exaggerated, thus giving rise to an increase in the thickness of the chip package structure 100.